Ex_phase2_intro:
.asciiz "\nAs a member of the Execution team you have the responsibility of desiging the execution state. This is the most verilog intensive section of the processor, as it includes the ALU."

code1:
.asciiz "\nCongratulations, you are a code writing beast. With ease you output code that would have most baffeled."
code2:
.asciiz "\nCongratulation, you have a code writing genius on your team, sit back and watch him do all the work for you" 

ex_phase2_question1:
.asciiz "\nIs you name Joshua Holland?\n1. Yes\n2. No"

phase2_ex_start:
	li $a0, Ex_phase2_intro
	jal libplp_uart_write_string
	nop
	
	li $a0, ex_phase2_question1
	jal libplp_uart_write_string
	nop
	
	# Yes, you are Josh
	# Fuck yeah I'm Josh
	move $t0, $v0
	li $t1, 0x00000031
	beq $t0, $t1, code1
	nop
	# no, you are not Josh
	move $t0, $v0
	li $t1, 0x00000032
	beq $t0, $t1, code2
	nop
	
code1:
	li $a0, JoshWriteCode
	jal libplp_uart_write_string
	nop
	jal combat_coinflip
	nop
	j integtationStall
	
code2:
	li $a0, watchJoshWriteCode
	jal libplp_uart_write_string
	nop
	jal combat_coinflip
	nop
	j integtationStall
	